Home Training Quartus II & Timing Analysis

Quartus Prime Foundation & Timing Analysis

Attention: open in a new window. PrintE-mail

Day 1 You will learn how to use the Quartus Prime® software to develop an FPGA or CPLD. You will create a new project, enter in new or existing design files, and compile your design. You will also learn about timing constraints and analyze a design compiled with these constraints using the TimeQuest timing analyzer, the path-based static timing analysis tool included with the Quartus II software. You will learn techniques to help you plan your design. You will employ Quartus Prime features that can help you achieve design goals faster. You will also learn how to plan and manage I/O assignments for your target device.

Day 2 You will learn how to constrain & analyze a design for timing using the TimeQuest timing analyzer in the Quartus® II software. This includes understanding FPGA timing parameters, writing Synopsys Design Constraint (SDC) files, generating various timing reports in the TimeQuest timing analyzer & applying this knowledge to an FPGA design. Besides learning the basic requirements to ensure that your design meets timing, you will see how the TimeQuest timing analyzer makes it easy to create timing constraints to help you meet those requirements.

At Course Completion

You will be able to:

  • Make pre-project decisions to plan design
  • Create, manage & compile Quartus Prime projects
  • Plan & manage device I/O assignments using Pin Planner
  • Assign clock & I/O constraints to improve design performance
  • Analyze clock & input/output timing using TimeQuest
  • Review compilation results
  • Understand the TimeQuest timing analyzer timing analysis design flow
  • Apply basic and complex timing constraints to an FPGA design
  • Analyze an FPGA design for timing using the TimeQuest timing analyzer
  • Write and manipulate SDC files for analysis and controlling the Quartus Prime compilation


Skills required

Background in digital logic design
Ability to describe a hardware system using VHDL, Verilog or EDA schematic tool
Experience with PCs and the Windows operating system

Vendor Dependence


What's Included

This is what you get, when you take this course:

  • Two full days of expert training (in English or local language if possible)
  • Lab exercises (bring a USB stick to take the results home)
  • Binder with all training material in English
  • Coffee/the/water + fruit, pastries and a full lunch
  • Opportunity to network with industry colleagues

Registration and more information

If you want to sign up please contact Axcon: Tel. +45 4822 9266 or email This e-mail address is being protected from spambots. You need JavaScript enabled to view it This e-mail address is being protected from spambots. You need JavaScript enabled to view it

Back to training schedule