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PCI Express x1 controller IP core for FPGA (Xilinx, Altera, Lattice etc.)

Get the VHDL source for a x1 PCIe endpoint IP core compliant to the PCI Express Base specification 1.1, with all 3 layers. The internal interface is either a simple 32 bit/125 MHz direct interface or - even more convinient - a DMA engine.

The compact and efficient core has been designed for x1 (single lane), high bandwidth and low latency use in embedded systems. All unneeded complexity has been stripped out, so you get a core that is highly optimized for the task and much simpler to work with.

Important simplifications are:

  • Designed for x1 (single lane) only
  • One virtual channel (VC) only - who really needs more?
  • No plug-fest certification - so this is best for systems where you define the "motherboard" (embedded systems)
The core easily fits even the low cost FPGA's like Altera Cyclone and Xilinx Spartan with lots of room for aditional functionality.

You get the source code

We all hate closed source IP. It's difficult to debug. You become dependent on external support. You can't inspect the code for design issues and code quality.

We want you to be sure you can allways fix any issues that may pop up down the line. That's why we decided to give you the full source code. At a price you can afford.

This gives you a number of unique advantages:

  • You are in control - now and forever
  • Retarget to any device
  • Change, expand, modify any part

The VHDL source code is clean, latch-free and well commented. Designed by experienced FPGA developers, and is in use in real world shipping products. The design was completed in 2007, with no major revisions required.

PHY Interface

The PHY interface code is "outside" the core. We have examples for 8 bit PIPE interface, internal PHY and others are fairly easy to create. You can do that - or we can help you.

User logic interface

The user logic is interfaced using a simple 125 MHz / 32 bit interface. For convinience and even simpler interfacing, a simple and efficient DMA engine is available as well.

The design strikes a good balance between simple integration and high efficiency. The simplest user logic design is very easy to design - yet the max bandwith of a single lane PCIe bus can be fully utilized.

Small PCIe

Example configurations take up very little FPGA logic and resources.

Target Device Slice/LE % MemBlks %
Altera Cyclone II 2C35-6 4400 13% 16 16%
Xilinx Spartan 3 3S1000-5 2700 35% 4 16%

The core is easily retargeted to other FPGA device families including Altera Stratix, Altera Arria, Xilinx Virtex, Lattice etc.

PCIe core datasheet

The product brief is available in pdf format:

Download: PCIe FPGA Core Product Brief

Contact us for a live demonstration.

More information in the product section: PCIe FPGA Core

PCIe Core Downloads

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