PCIe FPGA Core

The PCIe (PCI express) FPGA IP core is a compact, efficient vendor independent single lane PCI Express core for FPGA targeted low cost implementations using external PHY.

Why would you want to use this core?

• No integration or support worries - we give you the source code!
• Tight and fast - full bandwith in less gates.
• Drivers for both Linux and Windows.

PCI Express x1 FPGA Core Features

The main features for the PCIe core are:

• Designed for endpoints with x1 lane support.
• PCI Express 1.1 compliant.
• Support for 1 virtual channel (VC).
• Configurable payload buffer size (128 to 4096 bytes).
• Easy to use, efficient 32 bit/125 MHz user logic interface.
• Implements all three layers: Physical, Link and Transaction layers.
• Supports memory, I/O, configuration and message transactions.
• Supports user implemented configuration registers.
• Internal PHY or PIPE interface for external PHY device.
• Optimized for size, low latency and high throughput.
• Optional DMA engine included.
• High bandwidth Windows/Linux drivers available.
• 3rd party evaluation kit available.
• FPGA vendor independent VHDL design.
• Customization services available.

This core is written in clean and solid VHDL by experienced developers tested in real world shipping products.

Download: PCIe FPGA Core Product Brief (pdf)