VHDL for FPGA Designers

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Learn efficient VHDL for FPGA designers in just 2 days. Focus on practical RTL level design that performs well in synthesis. This course goes all the way to parameterized design and test benches for simulation. Coding style is covered as part of the key to successful FPGA designs.

Day 1 is based on Axcon's own training material and is designed to take you up to the level of being able to design useful VHDL for synthesis to real FPGA designs.

Day 2 is based on Altera's material and you will learn & practice efficient coding techniques for VHDL synthesis. You will gain experience writing behavioral & structural code & learn to effectively code common logic functions including registers, memory & arithmetic functions. You will use VHDL constructs to parameterize your designs to increase their flexibility and reusability. While the concepts presented will mainly be targeting Altera® devices using the Quartus® II software environment, many can be applied to synthesizing hardware using other synthesis tools as well. You will also be introduced to testbenches, VHDL constructs used to build them & common ways to write them. The hands-on exercises will use Quartus II software to process VHDL code and ModelSim®-Altera software for simulation.

At Course Completion

You will be able to:

Develop coding styles for efficient synthesis when:

Skills required

Background in digital logic design
Understanding of synthesis and simulation processes

Vendor Dependence

Low

The tools used are from Altera (lab exercises are done in ModelSim/Altera Edition), and is almost identical to other vendors offerings. Focus of the training is on language and methods, not tools.

What's Included

This is what you get, when you take this course:

Registration and more information

If you want to sign up please contact Axcon: Tel. +45 4822 9266 or email This e-mail address is being protected from spambots. You need JavaScript enabled to view it


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