Quartus Prime Verification & Optimization
Day 1 You will learn features of the Quartus Prime® software that will enable you to verify your FPGA design*. You will learn how to simulate Intel IP and megafunctions in other EDA simulation tools and how to use NativeLink to simulate directly in the Quartus Prime software from 3rd-party tools. You will also estimate FPGA power consumption using tools found in the Quartus Prime software. You will use debugging tools available in the Quartus Prime software, such as the SignalTap® II embedded logic analyzer, In-System Sources & Probes, & the Logic Analyzer Interface. You will learn to select the correct tool to effectively debug your design. *Some (not all) features examined by this course apply to CPLD designs
Day 2 You will learn advanced features of the Quartus® II design software that will enable you to shorten your design cycle as well as improve your design performance and utilization. You will use the incremental compilation flow and LogicLock™ regions in the Quartus Prime software to reduce compile times and preserve performance on selected regions of your designs. You will obtain your design goals in the area of performance, resource usage and power consumption by using design strategies, HDL coding styles and Quartus Prime software settings. You will also learn how to manage compile times effectively.
At Course Completion
You will be able to:
- Analyze power consumption with the PowerPlay power analyzer
- Debug designs in-system using the SignalTap II embedded logic analyzer
- Connect internal debug nodes to an external logic analyzer using the Logic Analyzer Interface
- View & edit embedded memory contents using the In-System Memory Content Editor
- Make incremental design changes with Chip Planner
- Define physical region constraints for an FPGA design using LogicLock regions
- Manage user-defined design partitions using the Quartus Prime incremental compilation flow
- Apply incremental compilation to the top-down & bottom-up design flows
- Use Quartus Prime software settings to improve internal & I/O timing, reduce logic resource usage & lower power consumption
- Choose recommended HDL coding styles
- Run Design Space Explorer to select optimal setting for full or partial designs
Skills required
We recommend completing the following course: Quartus Prime - Foundation and Timing Analysis
Vendor Dependence
High
What's Included
This is what you get, when you take this course:
- Two full days of expert training (in English or local language if possible)
- Lab exercises (bring a USB stick to take the results home)
- Binder with all training material in English
- Coffee/the/water + fruit, pastries and a full lunch
- Opportunity to network with industry colleagues
Registration and more information
If you want to sign up please contact Axcon: Tel. +45 4822 9266 or email This e-mail address is being protected from spambots. You need JavaScript enabled to view it