Interfacing to External Memory

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You will learn to implement external memory interfaces with Altera® FPGAs & Quartus® II software. The course provides lecture & lab exercises to help you understand the design flows, your options, & the challenges you will face. Since Double Data Rate (DDR) interfaces are most prevalent, we will focus on implementing DDR3 memory interfaces. You will learn the memory interface options you have & how to implement a “High Performance” DDR SDRAM controller with auto-calibrating phy block. This type of memory controller exploits the ALTMEMPHY core to achieve the highest system bandwidth. You will also learn how to take advantage of the self-service resources available. This should improve your confidence that you can successfully complete a memory interfacing design.

At Course Completion

You will be able to:

Prerequisites

We recommend completing the following courses:
Quartus II - Foundation and Timing Analysis
Quartus II - Verification and Optimization

Skills Required

Background in digital logic design and memory device types
Working knowledge of the Quartus II software, especially the TimeQuest static timing analyzer
Some knowledge of how to use a hardware simulator (eg. Mentor Graphics ModelSim® software)

Vendor Dependence

Medium

What's Included

This is what you get, when you take this course:

Registration and more information

If you want to sign up please contact Axcon: Tel. +45 4822 9266 or email This e-mail address is being protected from spambots. You need JavaScript enabled to view it This e-mail address is being protected from spambots. You need JavaScript enabled to view it


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