Quartus II Foundation & Timing Analysis

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Day 1 You will learn how to use the Quartus® II software to develop an FPGA or CPLD. You will create a new project, enter in new or existing design files, and compile your design. You will also learn about timing constraints and analyze a design compiled with these constraints using the TimeQuest timing analyzer, the path-based static timing analysis tool included with the Quartus II software. You will learn techniques to help you plan your design. You will employ Quartus II features that can help you achieve design goals faster. You will also learn how to plan and manage I/O assignments for your target device.

Day 2 You will learn how to constrain & analyze a design for timing using the TimeQuest timing analyzer in the Quartus® II software. This includes understanding FPGA timing parameters, writing Synopsys Design Constraint (SDC) files, generating various timing reports in the TimeQuest timing analyzer & applying this knowledge to an FPGA design. Besides learning the basic requirements to ensure that your design meets timing, you will see how the TimeQuest timing analyzer makes it easy to create timing constraints to help you meet those requirements.

At Course Completion

You will be able to:

 

Skills required

Background in digital logic design
Ability to describe a hardware system using VHDL, Verilog or EDA schematic tool
Experience with PCs and the Windows operating system

Vendor Dependence

High

What's Included

This is what you get, when you take this course:

Registration and more information

If you want to sign up please contact Axcon: Tel. +45 4822 9266 or email This e-mail address is being protected from spambots. You need JavaScript enabled to view it This e-mail address is being protected from spambots. You need JavaScript enabled to view it


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